9-85 cat93cxxxx (1k-16k) supervisory circuits with microwire serial cmos e 2 prom, precision reset controller and watchdog timer description the cat93cxxxx is a single chip solution to three popular functions of eeprom memory, precision reset controller and watchdog timer. the serial eeprom memory of the 93cxxxx can be configured either by 16- bits or by 8-bits. each register can be written (or read) by using the di (or do pin). the reset function of the 93cxxxx protects the system during brown out and power up/down conditions. during system failure the watchdog timer feature protects the microcontroller with a reset signal. catalyst's advanced cmos technology substantially reduces device power requirements. the 93cxxxx is available in 8-pin dip, 8- pin tssop or 8-pin soic pack ages. it is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years. pin configuration block diagram pin functions pin name function cs chip select reset/ reset reset i/o sk clock input di serial data input do serial data output v cc +2.7 to 6.0v power supply gnd ground org memory organization note: when the org pin is connected to vcc, the x16 organiza tion is selected. when it is connected to ground, the x8 pin is selected. if the org pin is left unconnected, then an internal pullup device will select the x16 organization. 93cx61x 93cx62x 93cx63x features n watchdog timer n programmable reset threshold n built-in inadvertent write protection v cc lock out n high speed operation: 3mhz n low power cmos technology n x 16 or x 8 selectable serial memory n self-timed write cycle with auto-clear n sequential read n fast nonvolatile write cycle: 3ms max n active high or low reset outputs precision power supply voltage monitoring 5v, 3.3v and 3v options n hardware and software write protection n power-up inadvertant write protection n 1,000,000 program/erase cycles n 100 year data retention n commercial, industrial, and automotive temperature ranges n 2.7-6.0 volt operation n 16 byte page mode advanced information cs sk di do v cc reset( reset) org gnd 1 2 3 4 8 7 6 5 cs sk di do v cc wdi gnd 1 2 3 4 8 7 6 5 reset( reset) cs sk di do v cc reset gnd 1 2 3 4 8 7 6 5 reset v cc address decoder memory array data register mode decode logic clock generator output buffer do sk cs di org gnd reset controller high precision vcc monitor wdi reset/ reset watchdog ? 1998 by catalyst semiconductor, inc. characteristics subject to change without notice
9-86 advanced information cat93cxxxx stock no. 21084-01 2/98 absolute maximum ratings* temperature under bias....................C55 c to +125 c storage temperature........................ C65 c to +150 c voltage on any pin with respect to ground (1) ..............C2.0v to +v cc + 2.0v v cc with respect to ground..................C2.0v to +7.0v package power dissipation capability (ta = 25 c)1.0w.................................1.0w lead soldering temperature (10 secs)...............300 c output short circuit current (2) ..........................100ma comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. note: (1) the minimum dc input voltage is C0.5v. during transitions, inputs may undershoot to C2.0v for periods of less than 20 ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc + 2.0v for periods of less than 20ns. (2) output shorted for no more than one second. no more than one output shorted at a time. d.c. operating characteristics v cc = +2.7v to +6.0v, unless otherwise specified. limits symbol parameter min. typ. max. units test conditions i cc1 power supply current 3 ma f sk = 1mhz (write) v cc = 5.0v i cc2 power supply current 1 ma f sk = 1mhz (read) v cc = 5.0v i sb1 power supply current 10 m a cs = 0v (standby) (x8 mode) org=gnd i sb2 power supply current 0 m a cs=0v (standby) (x16mode) org=float or v cc i li input leakage current 1 m av in = 0v to v cc i lo output leakage current 1 m av out = 0v to v cc , (including org pin) cs = 0v v il1 input low voltage -0.1 0.8 v 4.5v v cc <5.5v v ih1 input high voltage 2 v cc +1 v v ol1 output low voltage 0.4 v 4.5v v cc <5.5v v oh1 output high voltage 2.4 i ol = 2.1ma vi oh = -400 m a
9-87 cat93cxxxx stock no. 21084-01 2/98 advanced information a.c. characteristics v cc =2.7v to 6.0v unless otherwise specified. output load is 1 ttl gate and 100pf power-up timing (1)(2) symbol parameter max. units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. (3) latch-up protection is provided for stresses up to 100 ma on address and data pins from C1v to v cc +1v. limits v cc =v cc = 2.7v -6v 4.5v-5.5v test symbol parameter min. max. min. max. units conditions t css cs setup time 250 50 ns t csh cs hold time 0 0 ns t dis di setup time 250 50 ns t dih di hold time 250 50 ns t pd1 output delay to 1 0.5 0.1 m s t pd0 output delay to 0 0.5 0.1 m s t hz (1) output delay to high-z 500 100 ns t ew program/erase pulse width 5 5 ms t csmin minimum cs low time 0.5 0.1 m s t skhi minimum sk high time 0.5 0.1 m s t sklow minimum sk low time 0.5 0.1 m s t sv output delay to status valid 0.5 0.1 m s sk max maximum clock frequency dc 1000 dc 3000 khz c l = 100pf capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v symbol test max. units conditions c i/o (1) input/output capacitance 8 pf v i/o = 0v c in (1) input capacitance 6 pf v in = 0v reliability characteristics symbol parameter min. max. units reference test method n end (1) endurance 1,000,000 cycles/byte mil-std-883, test method 1033 t dr (1) data retention 100 years mil-std-883, test method 1008 v zap (1) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (1)(3) latch-up 100 ma jedec standard 17
9-88 advanced information cat93cxxxx stock no. 21084-01 2/98 instruction set instruction device start opcode address data comments type bit x8 x16 x8 x16 read 93c46xx 1 10 a6Ca0 a5-a0 read address anCa0 93c56xx (1) 1 10 a8Ca0 a7-a0 93c66xx 1 10 a8Ca0 a7-a0 93c57xx 1 10 a7-a0 a6-a0 93c86xx 1 10 a10-a0 a9-a0 erase 93c46xx 1 11 a6Ca0 a5-a0 clear address anCa0 93c56xx (1) 1 11 a8Ca0 a7-a0 93c66xx 1 11 a8Ca0 a7-a0 93c57xx 1 11 a7-a0 a6-a0 93c86xx 1 11 a10-a0 a9-a0 write 93c46xx 1 01 a6Ca0 a5-a0 d7-d0 d15-d0 write address anCa0 93c56xx (1) 1 01 a8Ca0 a7-a0 d7-d0 d15-d0 93c66xx 1 01 a8Ca0 a7-a0 d7-d0 d15-d0 93c57xx 1 01 a7-a0 a6-a0 d7-d0 d15-d0 93c86xx 1 01 a10-a0 a9-a0 d7-d0 d15-d0 ewen 93c46xx 1 00 11xxxxx 11xxxx write enable 93c56xx 1 00 11xxxxxxx 11xxxxxx 93c66xx 1 00 11xxxxxxx 11xxxxxx 93c57xx 1 00 11xxxxxx 11xxxxx 93c86xx 1 00 11xxxxxxxxx 11xxxxxxxx ewds 93c46xx 1 00 00xxxxx 00xxxx write disable 93c56xx 1 00 00xxxxxxx 00xxxxxx 93c66xx 1 00 00xxxxxxx 00xxxxxx 93c57xx 1 00 00xxxxxx 00xxxxx 93c86xx 1 00 00xxxxxxxxx 00xxxxxxxx eral 93c46xx 1 00 10xxxxx 10xxxx clear all addresses 93c56xx 1 00 10xxxxxxx 10xxxxxx 93c66xx 1 00 10xxxxxxx 10xxxxxx 93c57xx 1 00 10xxxxxx 10xxxxx 93c86xx 1 00 10xxxxxxxxx 10xxxxxxxx wral 93c46xx 1 00 01xxxxx 01xxxx d7-d0 d15-d0 write all addresses 93c56xx 1 00 01xxxxxxx 01xxxxxx d7-d0 d15-d0 93c66xx 1 00 01xxxxxxx 01xxxxxx d7-d0 d15-d0 93c57xx 1 00 01xxxxxx 01xxxxx d7-d0 d15-d0 93c86xx 1 00 01xxxxxxxxx 01xxxxxxxx d7-d0 d15-d0 note: (1) address bit a8 for 256x8 org and a7 for 128x16 org are "don't care" bits, but must be kept at either a "1" or "0" for read, write and erase commands.
9-89 cat93cxxxx stock no. 21084-01 2/98 advanced information figure 1. reset output timing symbol parameter min. max. units t glitch glitch reject pulse width 100 ns v rt reset threshold hystersis 15 mv v olrs reset output low voltage (i olrs =1ma) 0.4 v v ohrs reset output high voltage vcc-0.75 v reset threshold (vcc=5v) 4.50 4.75 (93cxxxx-45) reset threshold (vcc=5v) 4.25 4.50 (93cxxxx-42) reset threshold (vcc=3.3v) 3.00 3.15 (93cxxxx-30) reset threshold (vcc=3.3v) 2.85 3.00 (93cxxxx-28) reset threshold (vcc=3v) 2.55 2.70 (93cxxxx-25) t purst power-up reset timeout 130 270 ms t rpd v th to reset output delay 5 m s v rvalid reset output valid 1 v reset circuit characteristics v th v glitch t v cc purst t purst t rpd t rvalid v v th reset reset rpd t
9-90 advanced information cat93cxxxx stock no. 21084-01 2/98 device operation reset controller description the cat93cxxxx provides a precision reset con- troller that ensures correct system operation during brown-out and power-up/down conditions. it is config- ured with open drain reset outputs. during power- up, the reset outputs remain active until v cc reaches the v th threshold and will continue driving the outputs for approximately 200ms (t purst ) after reach- ing v th. after the t purst timeout interval, the device will cease to drive reset outputs. at this point the reset outputs will be pulled up or down by their respective pull up/pull down devices. during power-down, the reset outputs will begin driving active when v cc falls below v th. the reset outputs will be valid so long as v cc is >1.0v (v rvalid ). the reset pins are i/os; therefore, the cat93cxxxx can act as a signal conditioning circuit for an externally applied reset. the inputs are level triggered; that is, the reset input in the 93cxxxx will initiate a reset timeout after detecting a high and the reset input in the 93cxxxx will initiate a reset timeout after detecting a low. watchdog timer the watchdog timer provides an independent protec- tion for microcontrollers. during a system failure, the cat93cxxxx will respond with a reset signal after a time-out interval of 1.6 seconds for lack of activity. as long as the reset signal is asserted, the watchdog timer will not count and will stay cleared. hardware data protection the 93cxxxx is designed with a v cc lock out data protection feature to provide a high degree of data integrity. the v cc sense provides write protection when v cc falls below the reset threshold value. the v cc lock out inhibits writes to the serial eeprom whenever v cc falls below (power down) or until v cc reaches the reset threshold (power up). reset threshold voltage from the factory the 93cxxxx is offered in five differ- ent variations of reset threshold voltages. they are 4.50-4.75v, 4.25-4.50v, 3.00-3.15v, 2.85-3.00v and 2.55-2.70v. to provide added flexibility to design engineers using this product, the 93cxxxx is de- signed with an additional feature of programming the reset threshold voltage. this allows the user to change the existing reset threshold voltage to one of the other four reset threshold voltages. once the reset threshold voltage is selected it will not change even after cycling the power, unless the user uses the programmer to change the reset threshold voltage. however, the programming function is available only through external program manufacturers. please call catalyst for a list of programmer manufacturers which support this function. memory functional description the cat93cxxxx is a 1024/2048/4096/16,384-bit non- volatile memory intended for use with industry standard microprocessors. the cat93cxxxx can be organized as either registers of 16 bits or 8 bits. when organized as x16, seven 9-bit instructions for 93c46xx; seven 10-bit instructions for 93c57xx; seven 11-bit instructions for 93c56xx and 93c66xx; seven 13-bit instructions for 93c86xx; control the reading, writing and erase opera- tions of the device. when organized as x8, seven 10-bit instructions for 93c46xx; seven 11-bit instructions for 93c57; seven 12-bit instructions for 93c56 and 93c66: seven 14-bit instructions for 93c86; control the reading, writing and erase operations of the device. the cat93cxxxx operates on a single power supply and will generate on chip, the high voltage required during any write operation. instructions, addresses, and write data are clocked into the di pin on the rising edge of the clock (sk). the do pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. the ready/busy status can be determined after the start of a write operation by selecting the device (cs high) and polling the do pin; do low indicates that the write operation is not completed, while do high indicates that the device is ready for the next instruction. if necessary, the do pin may be placed back into a high impedance state during chip select by shifting a dummy 1 into the di pin. the do pin will enter the high impedance state on the falling edge of the clock (sk). placing the do pin into the high impedance state is recommended in applica- tions where the di pin and the do pin are to be tied together to form a common di/o pin. the format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit (93c46xx)//7-bit (93c57xx)/ 8-bit (93c56xx or 93c66xx)/10-bit (93c86xx) (an additional bit when organized x8) and for write operations a 16-bit data field (8-bit for x8 organizations).
9-91 cat93cxxxx stock no. 21084-01 2/98 advanced information figure 2. sychronous data timing sk di cs do t dis t pd0, t pd1 t csmin t css t dis t dih t skhi t csh valid valid data valid t sklow read upon receiving a read command and an address (clocked into the di pin), the do pin of the cat93cxxxx will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (msb first). the output data bits will toggle on the rising edge of the sk clock and are stable after the specified time delay (t pd0 or t pd1 ) for the 93cxxxx, after the initial data word has been shifted out and cs remains asserted with the sk clock continuing to toggle, the device will automatically incre- ment to the next address and shift out the next data word in a sequential read mode. as long as cs is continu- ously asserted and sk continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. in the sequential read mode, only the initial data word is preceeded by a dummy zero bit. all subsequent data words will follow without a dummy zero bit. write after receiving a write command, address and the data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear and data store cycle of the memory location specified in the instruction. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93cxxxx can be determined by selecting the de- vice and polling the do pin. since this device features auto-clear before write, it is not necessary to erase a memory location before it is written into. page write the 93cxxxx writes up to 16 bytes (8 words for x16 format) of data in a single write cycle, using the page write operation. the page write operation is initiated in the same manner as the byte (word for x16 format) write operation. however, instead of terminating after the initial byte (word for x16 format) is transmitted, the host figure 3. read instruction timing sk cs di do high-z 11 0 a n a nC1 a 0 dummy 0 d 15 . . . d 0 or d 7 . . . d 0 1 11 1 111 11111111 address + 1 d 15 . . . d 0 or d 7 . . . d 0 address + 2 d 15 . . . d 0 or d 7 . . . d 0 address + n d 15 . . . or d 7 . . . don't care
9-92 advanced information cat93cxxxx stock no. 21084-01 2/98 can then continue to clock in 8-bit (16-bit for x16 format) data to be written to the next higher address. internally, the address pointer is incremented after each group of eight clocks (16 clocks for x16 format). if the host transmits more than 16 bytes (8 words for x16 format) the address counter wraps around and previously transmitted data will be overwritten. after receiving a write command, address and the data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear and data store cycle of the memory location specified in the instruction. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93cxxxx can be determined by selecting the de- vice and polling the do pin. since this device features auto-clear before write, it is not necessary to erase a memory location before it is written into. erase upon receiving an erase command and address, the cs (chip select) pin must be deasserted for a minimum of t csmin . the falling edge of cs will start the self clocking clear cycle of the selected memory location. the clock- ing of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busy status of the cat93cxxxx can be determined by selecting the device and polling the do pin. once cleared, the content of a cleared location returns to a logical 1 state. figure 5. erase instruction timing figure 4. write instruction timing sk cs di do t cs standby high-z high-z 101 a n a n-1 a 0 d n d 0 busy ready status verify t sv t hz t ew sk cs di do standby high-z high-z 1 a n a n-1 busy ready status verify t sv t hz t ew t cs 11 a 0
9-93 cat93cxxxx stock no. 21084-01 2/98 advanced information figure 6. ewen/ewds instruction timing sk cs di standby 10 0 * * enable=11 disable=00 entered the self clocking mode. the ready/busy status of the cat93cxxxx can be determined by selecting the device and polling the do pin. once cleared, the contents of all memory bits return to a logical 1 state. write all upon receiving a wral command and data, the cs (chip select) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking data write to all memory locations in the device. the clocking of the sk pin is not necessary after the device has entered the self clocking mode. the ready/busystatus of the cat93cxxxxcan be determined by selecting the device and polling the do pin. it is not necessary for all memory locations to be cleared before the wral com- mand is executed. erase/write enable and disable the cat93cxxxx powers up in the write disable state. any writing after power-up or after an ewds (write disable) instruction must first be preceded by the ewen (write enable) instruction. once the write instruction is enabled, it will remain enabled until power to the device is removed, or the ewds instruction is sent. the ewds instruction can be used to disable all cat93cxxxx write and clear instructions, and will prevent any acci- dental writing or clearing of the device. data can be read normally from the device regardless of the write enable/ disable status. erase all upon receiving an eral command, the cs (chip se- lect) pin must be deselected for a minimum of t csmin . the falling edge of cs will start the self clocking clear cycle of all memory locations in the device. the clocking of the sk pin is not necessary after the device has figure 7. eral instruction timing sk cs di do standby t cs high-z high-z 10 1 busy ready status verify t sv t hz t ew 00
9-94 advanced information cat93cxxxx stock no. 21084-01 2/98 ordering information figure 8. wral instruction timing status verify sk cs di do standby high-z 10 1 busy ready t sv t hz t ew t cs d n d 0 0 0 package p = pdip s = soic (jedec) j = soic (jedec) k = soic (eiaj) u = tssop prefix device # suffix 93c46 s i te13 product number 93c46: 1k 93c56: 2k 93c57: 2k 93c66: 4k 93c86: 16k tape & reel te13: 2000/reel -25 cat temperature range blank = commercial (0? - 70?c) i = industrial (-40? - 85?c) a = automotive (-40? - 105?c)* * -40? to +125?c is available upon request reset threshold voltage 45: 4.5-4.75v 42: 4.25-4.5v 30: 3.0-3.15v 28: 2.85-3.0v 25: 2.55-2.7v optional company id product variation 11 reset on pin 7, no wdt 12 reset on pin 7, no wdt 13 reset on pin 7, wdt on cs 14 reset on pin 7, wdt on cs 21 x16 mode, reset on pin 7 22 x16 mode, reset on pin 7 23 x8 mode, reset on pin 7 24 x8 mode, reset on pin 7 31 x16 mode, no wdt 32 x8 mode, no wdt 33 x16 mode, wdt on cs 34 x8 mode, wdt on cs 11 note: (1) the device used in the above example is a 93c4611si-25te13 (1k eeprom, reset on pin 7 & no wdt, soic, industrial temperatur e, 2.55v to 2.7 v reset threshold voltage, tape & reel).
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